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We propose an environment for the verification of analog circuits behavioral properties, where the circuit state space bounds are first computed using qualitative simulation. Then, their specified behavioral properties are verified on these bounds. The effectiveness of the method is illustrated with a tunnel diode oscillator.
This paper presents a novel approach for improving automated analog yield optimization using a two step exploration strategy. First, a global optimization phase relies on a modified Lipschitizian optimization to sample the potential optimal sub-regions of the feasible design space. The search locates a design point near the optimal solution that is used as(More)
This paper presents an approach for enhancing analog circuit sizing using Satisfiability Modulo Theory (SMT). The circuit sizing problem is encoded using nonlinear constraints. An SMT-based algorithm exhaustively explores the design space, where the biasing-level design variables are conservatively tracked using a collection of hyperrectangles. The device(More)
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