Ondrej Subrt

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—A step-by-step design procedure of sub-bandgap voltage reference (BGR) is proposed. The procedure shows on example structure main design steps of crucial parameters verified later by a simulation. The block is meant to be fabricated in 0.35µm CMOS process with analog options. The main features of the concept are the sub-bandgap output voltage of 0.7V, low(More)
This work presents an thorough analysis and design of a low-voltage low-power voltage reference circuit with sub-bandgap output voltage. The outcome of the analysis and the resulting design rules are universal and it is supposed to be general and suitable for similar topologies with just minor modifications. The general analysis is followed by a selection(More)
483 patients were operated on one of the percutaneous method. The radiofrequency thermocoagulation, the application of glycerol to the trigeminal cistern and the balloon compression of the ganglion were used. There are no substantial differences in the results and number of recurrences obtained with any of the different lesions. The choice of the type of(More)
− One of the recent approaches to test A/D converter performance is the so-called Servo-Loop Method. This method is aimed at the non-linearity extraction of static ADC transfer curve. In this paper, we prove an advanced Servo-Loop version focusing on behavioral and transistor-level example of the Residual Signed Digit (RSD) cyclic A/D converter design. The(More)
A b s t r a c t – This paper deals with a prospective approach of modeling and design evaluation applied to pipelined A/D converter architecture. In contrast with conventional ADC modeling algorithms targeted to extract the maximum ADC non-linearity error, the innovative approach presented allows to decompose magnitudes of individual error sources from a(More)
This paper deals with the virtual testing environment for analog-to-digital converters (ADCs) employing a novel and powerful extension of the Servo-Loop method [1], [4]. We build an improved version of the Servo-Loop targeted to full transistor-level circuit simulation of static integral and differential ADC non-linearity. In comparison with the(More)