First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. This thesis presents an encompassing description of the motivation and design… (More)
Modern applications increasingly require the computation of DSP workloads comprised of a variety of numerically-intensive DSP tasks. These workloads are found in communication, multime-dia, embedded, and wireless applications, and often require very high levels of computation and high energy efficiency. The Asynchronous Array of Simple Processors (AsAP)… (More)
as a JPEG encoder core and a fully compliant IEEE 802.11a/g wireless LAN baseband transmitter.
A software based IEEE 802.11a digital baseband transmitter has been implemented on a highly parallel single-chip DSP. The processing platform is a programmable and reconfigurable asynchronous array of simple processors (AsAP) that is well matched to complex system workloads such as 802.11a. The transmitter is the first fully-compliant 802.11a software… (More)
This paper presents the architecture of an asynchronous array of simple processors (AsAP), and evaluates its key architectural features as well as its performance and energy efficiency. The AsAP processor calculates DSP applications with high energy-efficiency, is capable of high-performance, is easily scalable, and is well-suited to future fabrication… (More)
Fast Fourier Transforms are used in a variety of Digital Signal Processing applications. As semiconductor process technology becomes more refined, the ability to implement faster and more efficient FFTs increases. However, due to the high costs and design time of custom FFT processors, implementation of the FFT on pro-grammable or reconfigurable platforms… (More)
Outline • Motivation and key features • Architectural details • The AsAP chip and results • Programming and applications • Conclusion
The design of an asynchronously shared memory module for the AsAP platform is presented. AsAP consists of a 2-dimensional array of processing elements with limited memory resources. The memory module expands the storage capacity available to AsAP processors, enabling the mapping of applications with large working sets. The memory module described shares an… (More)