Omar Al-Kharji Al-Ali

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This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock(More)
An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in(More)
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This paper presents a new circuit topology of a phase-locked loop that can be used for synchronising a single-phase wind turbine generator (WTG) with the low voltage utility grid. The circuit is based on the time-delay digital tanlock loop (TDTL) architecture and was modelled and simulated using Simulink/MATLAB. The results presented demonstrate the ability(More)
This paper presents a novel design of a digital phase lock loop based on the digital tanlock loop (DTL) architecture. The new simplified design eliminates the requirement for a delay block. Instead, it incorporates an adaptation mechanism whose output feeds into the phase detector block of the new design and controls the acquisition time and locking range(More)
This paper proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The π 2 ⁄ (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time delay digital tanlock loop (TDTL), is preserved by using two quadrature sampling signals for the loop channels. The proposed(More)
This paper presents an improved second-order time delay digital tanlock loop (TDTL) system. It uses an initialization technique to enhance some of the main performance parameters of the original TDTL loop and hence overcome some of the inherent loop limitations. A one-bit Sigma-Delta modulator is used to initialize the DCO (digital controlled oscillator)(More)
This paper presents an improved digital tanlock loop architecture that has linear phase detector characteristics. These characteristics were linearized by removing the fixed time delay unit in the original time delay tanlock loop (TDTL) and using a modified DCO (digital controlled oscillator). The modified DCO incorporates lookup tables to generate two(More)