Omar Al-Kharji Al-Ali

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An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in(More)
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This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock(More)
This paper proposes an improved time delay digital tanlock loop (TDTL) system in which a feedforward loop is used to initialize the loop filter memory so as to enhance the acquisition speed of the system. The feedforward loop is used to estimate the value of the steady-state frequency of the input signal which is subsequently loaded into the memory of the(More)
A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction(More)
The design of a second-order digital phase-locked loop (DPLL) based on the time-delay digital tanlock loop (TDTL) architecture is presented. The proposed design simplifies the architecture of the TDTL by eliminating the requirement for the time delay block. In addition, the system includes a controller block whose output feeds into the arctan phase detector(More)