Omar Al-Kharji Al-Ali

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An adaptive initialization process for the first-order time delay digital tanlock loop (TDTL) is proposed. The process results in improving the system performance by widening its lock range and by having zero steady-state phase error. The proposed adaptive TDTL with zero phase error (ATDTL-ZPE) uses a feedforward initialization technique which results in(More)
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This paper presents the architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage utility grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock(More)
This paper presents a novel design of a digital phase lock loop based on the digital tanlock loop (DTL) architecture. The new simplified design eliminates the requirement for a delay block. Instead, it incorporates an adaptation mechanism whose output feeds into the phase detector block of the new design and controls the acquisition time and locking range(More)
This paper presents a new circuit topology of a phase-locked loop that can be used for synchronising a single-phase wind turbine generator (WTG) with the low voltage utility grid. The circuit is based on the time-delay digital tanlock loop (TDTL) architecture and was modelled and simulated using Simulink/MATLAB. The results presented demonstrate the ability(More)
A dual Time Delay Digital Tanlock Loop (D-TDTL) topology is proposed in this work. The system consists of a stacked dual loop of which the top one acts as a Frequency Lock loop (FLL) for the bottom loop, while the latter is a phase lock loop (PLL) that enhances the overall phase of the system. The main advantage of the proposed system is the large reduction(More)
This paper proposes two circuit topologies for acquisition enhancement in a time delay digital tanlock loop (TDTL). They are based on feedforward (FF) and feedback (FB) control schemes. Both schemes are used to improve the acquisition speed of the conventional TDTL by employing an auxiliary circuit. The ultimate objective of the FB and FF techniques is to(More)