Oluleye Olorode

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The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40(More)
The increasing demand for wearable medical devices, coupled with their short battery life, has led to a renewed interest in low power processors. A significant proportion of the total power consumed by these medical device processors, occur in the memory systems, and therefore the focus of sour work. In this paper, we propose a technique that reduces the(More)
Recent advances in computer processor design have led to the introduction of sub-blocking to cache architectures. Sub-block caches reduce the tag area and power overhead in caches without reducing the effective cache size by using fewer tags to index the full data RAM array. In spite of achieving reduced area and power overhead, sub-block caches suffer(More)
Recent advances in processor architecture have led to the introduction of sub-blocking to cache architectures. Sub-blocking reduces the tag area and power overhead in caches without reducing the effective cache size, by using fewer tags to index the full data RAM array. But they suffer from performance degradation due to cache pollution. We propose(More)
We propose a technique that reduces static power consumption in caches with negligible hardware overhead and no performance penalties. Our proposed architecture achieves this by deterministically lowering the power state of cache lines that are guaranteed not to be accessed in the immediate future by exploiting in-flight cache access information. We(More)
Various models featuring horizontal wells with multiple fractures have been proposed to characterize flow behavior over time in tight and shale gas systems. Currently, only very little is known about the effects of nonideal fracture patterns and coupled primary-secondary fracture interactions on reservoir performance in unconventional gas reservoirs. We(More)
Low to ultralow permeability formations require "special" treatments/stimulation to make them produce economical quantities of hydrocarbon and at the moment, multi-stage hydraulic fracturing (MSHF or MHF) is the most commonly used stimulation method for enhancing the exploitation of these reservoirs. Recently, the slot-drill (SD) completion technique was(More)
The increasing demand for high speed and low power memory systems has led to the introduction of Ternary Content Addressable Memories to cache architectures, because of their ability to store the don’t care value in addition to 1’s and 0’s. However, existing simulator platforms have been built to support SRAM and DRAM based memory models. In this paper, we(More)
Cache memory systems consume a significant portion of static and dynamic power consumption in processors. Similarly, the access latency through the cache memory system significantly impacts the overall processor performance. Several techniques have been proposed to tackle the individual power or performance. However, almost all trade off performance for(More)
Low power design has become an important design requirement in any deep-submicron CMOS design development. State retention using retention flip flops is one of the low power techniques that offer the ability to save and restore the state of the design during a period of inactivity (IDLE or STANDBY mode). Since processor cores typically have a well-defined(More)
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