Olivier Weber

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P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, J. Mazurier, O. Weber, F. Andrieu, L. Tosti, L.Brevard, B. Sklenard, P. Coudrain, S. Bobba, H. Ben Jamaa, P-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. De Micheli, S. Deleonibus, O. Faynot and T. Poiroux. CEAleti, Minatec Campus,(More)
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
L. Pasini, P. Batude, J. Lacord, M. Casse, B. Mathieu, B. Sklenard, F. Piegas Luce, J. Micout, A. Payet, F. Mazen, P. Besson, E. Ghegin, J. Borrel, R. Daubriac, L. Hutin, D. Blachier, D. Barge, S. Chhun, V. Mazzocchi, A. Cros, J-P. Barnes, Z. Saghi, V. Delaye, N. Rambal, V. Lapras, J. Mazurier, O. Weber, F. Andrieu, L. Brunet, C. Fenouillet-Beranger, Q.(More)
As a part of the MICROBENT programme, an investigation of the sedimentation framework was carried out at the water-sediment interface in the Thau Lagoon (French Mediterranean coast). Two main sites, C4 in the middle of the lagoon and C5 near oyster farms, were visited six times between December 2001 and May 2003. Interface sediments were studied using(More)
We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on(More)
We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data(More)
We show that planar Fully Depleted Silicon-OnInsulator (FDSOI) technology allows improving the threshold voltage VT variability of CMOS devices in comparison to standard bulk CMOS devices. Moreover, integrated on UltraThin Body and Buried oxide (UTBB), it enables the use of standard power management techniques (Reverse or Forward Back Biasing) without VT(More)
For the first time, we report fully depleted SOI MOS transistors with WSi<sub>x</sub> gate on HfO<sub>2</sub>. Gate work function, dielectric properties and channel mobility are presented in terms of Si/W ratio and compared to TiN gate devices. A 35% electron mobility gain was obtained with a WSi<sub>x</sub> gate device as compared to a TiN gate transistor.(More)