Olivier Weber

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3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance(More)
—This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data(More)
OATAO is an open access repository that collects the work of Toulouse researchers and makes it freely available over the web where possible. Abstract As a part of the MICROBENT programme, an investigation of the sedimentation framework was carried out at the water-sediment interface in the Thau Lagoon (French Mediterranean coast). Two main sites, C4 in the(More)
For the first time, we report fully depleted SOI MOS transistors with WSi<sub>x</sub> gate on HfO<sub>2</sub>. Gate work function, dielectric properties and channel mobility are presented in terms of Si/W ratio and compared to TiN gate devices. A 35% electron mobility gain was obtained with a WSi<sub>x</sub> gate device as compared to a TiN gate transistor.(More)
We demonstrate that Fully Depleted Silicon-On-Insulator (FDSOI) technology is a simple and mature alternative to the bulk one for the 22nm technology node and beyond. In particular, this technology allows significant improvement of the transistors electrostatic control and variability. Furthermore, the integration of such FDSOI transistors on an ultra-thin(More)
Thin film devices (FDSOI) are among the most promising candidates for next device generations due to their better immunity to short channel effects (SCE). In addition, the introduction of high-k and metal gate has greatly improved the MOSFETs performance by reducing the electrical oxide thickness (CET) and gate leakage current. However, if midgap metal gate(More)
We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM(More)