— This paper is devoted to a low-complexity algorithm for retiming circuits without cycles, i.e., those whose network graph is a direct acyclic graph (DAG). On one hand, DAG's have a great practical importance, as shown by the on-line arithmetic circuits used as a target application in this paper. On the other hand, retiming is a costly design optimization… (More)
Integer Linear Programming (ILP) is commonly used in high level and system level synthesis. It is an NP-Complete problem (in general cases). There exists some tools that give an optimal solution for small ILP formulations. Nevertheless, these tools may not give solutions for complex formulations. In this paper, we present a solution to overcome the problem… (More)
CAD tools for special purpose architecture usually use conventional radix 2 number system to represent integers. However, DSP designer expertise shows that redundant number systems improve the delay of arithmetic operations. In this paper, we come to the conclusion that arithmetic operator outputs have to be redundant whereas inputs have not. Therefore, an… (More)
This paper aims at addressing a particular aspect of multi-objective optimization problems in Electronic Design Automation (EDA). More specifically, we will present our study of the impact on quality and performance of evolutionary algorithms initial solutions. A new scheme for initial population generation is presented, which improves the quality and… (More)
Summary form only given. We present a way to automatically select, within an architectural synthesis tool, the best operand and operator number systems, in order to find the best speed/area tradeoff. This implies the use of different number systems (redundant and non-redundant) for the same design: this is what we call mixed arithmetics. We present an… (More)
Thermal distribution has become an important reliability concern for today's integrated circuits. In traditional design flows, the temperature of the chip is assumed to be uniform across the substrate. However, non-uniform thermal distribution can be a major source of inaccuracy in delay and clock skew computations, and can have an impact on… (More)
In this paper, we present a new methodology for structure optimization of block-based design. Instead of merging area and delay criteria, we segregate them into two independent steps. Solutions optimized for delay in the first step are optimized for area with a block-sizing algorithm in the second step. The fully optimized solutions eventually return to the… (More)
Floorplanning is an important step of IC design. Traditionally, floorplan representation has been segregated between slicing and non-slicing structures. We present a heuristic that translates any arbitrary structure into a slicing one, topologically equivalent to the initial one after a 1-D compaction.