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Journals and Conferences
This paper reviews the application of SCR-based ESD protection circuits in advanced CMOS/SOI technologies. The devices are integrated in a flexible modular circuit design technique allowing for independent optimization of key characteristics. The IC application focus is on sensitive IOs, i.e. (ultra-)thin GOX input protection and robust output driver design… (More)
This paper introduces an SCR based ESD protection design for SOI technologies. It is explained how efficient SCR devices can be constructed in SOI. These devices outperform MOS devices by about 4 times. Experimental data from 65 nm and 130 nm SOI is presented to support this.
HBM and MM are important standards for ESD testing and typically correlate well. In some notable cases however, MM shows much lower failure levels than HBM. One of the most important physical mechanisms responsible for this is dynamic avalanching. This paper provides an example of such a dynamic avalanching failure, and includes a description of the physics… (More)
The bipolar nature of ESD pulses such as MM introduces failure mechanisms that cannot be reproduced by TLP/HBM. A lowered breakdown voltage due to dynamic avalanching was observed. The key issue is that carriers injected during the first swing remain in the device after the current switches polarity. A case study for high-voltage diodes is presented.
This paper presents a novel approach to reduce the parasitic capacitive loading of RF and high speed digital interfaces by up to 35%. Unlike in the classic dual diode protection, both junctions connected to the pad are used in every stress combination.
Self protective output drivers have been used extensively as an elegant solution against Electro Static Discharge. However, recent measurement data show unexpectedly low HBM and MM results in low resistive EPI technologies. The HBM-TLP correlation issue is investigated and a novel local parallel protection scheme for output drivers is presented, solving the… (More)