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System on a chip (SOC) implementations typically require their functional blocks to run at different clock frequencies in order to better optimize the system performance for a wide variety of applications while staying within the power envelope. The functional blocks are required to exchange data between themselves and with off-chip memory through a shared(More)
A fast and reliable design tool for real-time simulation of clock grids is presented here. Its implementation is orders of magnitude faster than SPICE, which makes it well-suited for the analysis of a multitude of design options early in a project. The mathematical formulation fully models a regular RLC clock grid with arbitrarily located loads and input(More)
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