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3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage(More)
3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance(More)
Low field mobility in doubleand single-gate structures is analyzed for (100) and (110) SOI substrate orientation. A Monte Carlo algorithm for vanishing driving fields allows the calculation of the mobility for arbitrary scattering rates and band structure without further approximations. Due to volume inversion, mobility in double-gate ultra-thin body (110)(More)
—This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed(More)
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I<sub>OFF</sub> (&lt; 20 pA/mum) and high I<sub>ON</sub> (&gt; 2.2(More)
RF small-signal performances of Ultra-Thin Body and Box FDSOI transistors are evaluated using state-of-the-art 4-port characterization in the 100MHz-24GHz frequency range. Front-Gate cut-off frequencies and related figures of merit are extracted to assess the capabilities of the technology at 28 nm technology node for RF applications. Back-Gate cut-off(More)
In this paper we present a methodology allowing an emulated-3D two tiers physical implementation of any design using 2D commercial tools. Place and Route is achieved through similar steps as required by 2D designs: pre clock tree synthesis (including placement), clock tree synthesis and routing; to which we added a folding step in order to emulate the 3D(More)