Olivier Faynot

Learn More
3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage(More)
P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, J. Mazurier, O. Weber, F. Andrieu, L. Tosti, L.Brevard, B. Sklenard, P. Coudrain, S. Bobba, H. Ben Jamaa, P-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. De Micheli, S. Deleonibus, O. Faynot and T. Poiroux. CEAleti, Minatec Campus,(More)
This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal–oxide–semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were(More)
Low field mobility in doubleand single-gate structures is analyzed for (100) and (110) SOI substrate orientation. A Monte Carlo algorithm for vanishing driving fields allows the calculation of the mobility for arbitrary scattering rates and band structure without further approximations. Due to volume inversion, mobility in double-gate ultra-thin body (110)(More)
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low I<sub>OFF</sub> (&lt; 20 pA/mum) and high I<sub>ON</sub> (&gt; 2.2(More)
Compact MOS models based on surface potential are now firmly established, but for practical applications there is no reliable link between measured values of threshold voltage and the flat-band voltage on which such models are based. This brief presents an analytical relationship which may be implemented in compact models to provide a reliable and accurate(More)
This paper investigates the vulnerability of several micro- and nano-electronic technologies to a mixed harsh environment including high total ionizing dose at MGy levels and high temperature. Such operating conditions have been revealed recently for several applications like new security systems in existing or future nuclear power plants, fusion(More)
A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed(More)
We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on(More)