Olivier Domerego

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—Two formats for specifying power intent are currently in wide use in the industry today and as designers continue to strive for more power efficient designs new issues arise that need new solutions to improve on today's standards. This panel will discuss areas for improving today's power formats and the direction that these formats need to move, in order(More)
Leakage power management, wireless SoC In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-uA range(More)
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