Olivier Billoint

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Microelectrode arrays (MEAs) offer a powerful tool to both record activity and deliver electrical microstimulations to neural networks either in vitro or in vivo. Microelectronics microfabrication technologies now allow building high-density MEAs containing several hundreds of microelectrodes. However, dense arrays of 3D micro-needle electrodes, providing(More)
A 64 channels CMOS chip dedicated to in-vitro simultaneous recording and stimulation of neurons using microelectrode arrays has been developed. It includes, for each channel, a low noise, variable gain (10, 75 or 750), 0.08 Hz-3 kHz bandwidth measurement path with unity-gain for lower frequencies to allow measurement of the electrochemical potential. A(More)
In order to understand the dynamics of large neural networks, where information is widely distributed over thousands of cells, one of today's challenges is to successfully record the simultaneous activities of as many neurons as possible. This is made possible by using microelectrodes arrays (MEAs) positioned in contact with the neural tissue. Thanks to(More)
Todays' MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices(More)
This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps.(More)
In order to understand the dynamics of large neural networks, where information is widely distributed over thousands of cells, one of today's challenges is to successfully monitor the simultaneous activity of as many neurons as possible. This is made possible by using the Micro-Electrode Array (MEA) technology allowing neural cell culture and/or tissue(More)
In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and reconfigurable 10 ×10 ADPLL network is described, designed for prototyping distributed clock generation in large synchronous system(More)
3D Monolithic Integration (3DMI) technology provides very high dense vertical interconnects with low parasitics. Previous 3DMI design approaches provide either cell-on-cell or transistor-on-transistor integration. In this paper we present 3D Cell-on-Buffer (3DCoB) as a novel design approach for 3DMI. Our approach provides a fully compatible sign-off(More)