Oliver Chiu-sing Choy

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This paper presents a design of multiplier for the multiplication of two 8-bit two-complement numbers. The multiplier applies the self-timed asynchronous methodology such that the multiplier can be assumed to operate on average case delay. Also, modified Booth's algorithm is used to reduce the number of partial products generated. As a result, the speed of(More)
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufactuing cost, speed, power and area. In this paper, we present a novel VPGA logic cell, the complementary universal logic gate (CULG) which can be used to implement both sequential and(More)
This paper describes an asynchronous onedimensional order-8 integer cosine transform chip, which can calculate either forward or inverse transforms. The chip’s performance is maximized with a fast computation algorithm and the self-timed circuit technique. The basic self-timed block is a microcoded programmable processor. Eight of these processors are used(More)