The influence of the via bottom geometry on stress development in Cu interconnects is investigated by FE-Simulation. The mechanical characterization shows the weakest link concerning the reliability of the different via geometries. The via with the cone-shaped bottom seems to have the best reliability with respect to mechanical stress.
In this paper we present a model to generate voltage acceleration (Vacc) values from VRDB measurements with different ramp rates. The results have been verified with TDDB measurements.
In this paper we showed results on high temperature storage tests performed on 90nm, 65nm and 45nm node material with different back end of line stacks. We have seen a strong impact of BEOL stack up on resistance traces of tests at temperature of over 250°C for 1000h. We found that the detected resistance increases are not related to stress migration… (More)