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The superposition procedure modification - topological fault simulation method is offered. It lies in backtracing of defects on topology of the circuit. It is oriented on gate-level description of the circuits. According to it, the set of reconvergent fan-outs and tree-like structures are being defined in the description of the device.
The paper describes the CAD tools for CORDIC IP cores generation. It gives an opportunity for user to generate fully synthesizable, verified VHDL modules, which can be further used in digital systems design.
This paper presents Gaussian and non-Gaussian scenarios for the renormalized solutions of fractional integro-differential equations of Volterra type. The solutions are obtained under random initial conditions which are subordinated to chi-square random fields with weak or strong dependence.
System of Synthesis and Verification of Hardware Models-Formulas for Series Summation in Reproducing Kernel Hilbert Space (RKHS) which allows to carry out input of the description of the model-formula with the help of the GUI-interface is discovered. The examples of synthesis and experience data are represented. Market attractiveness and applications are… (More)