Olaf van der Sluis

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For the development of state-of-the-art Cu/low-k CMOS technologies, the integration and introduction of new low-k materials are one of the major bottlenecks due to the bad thermal and mechanical integrity of these materials and the inherited weak interfacial adhesion. Especially the forces resulting from packaging related processes such as dicing, wire(More)
Due to the miniaturization of integrated circuits, their thermo-mechanical reliability tends to become a truly critical design criterion. Especially the introduction of copper and low-k dielectric materials cause some reliability problems. Numerical simulation tools can assist developers to meet this challenge. This paper considers the first bond integrity(More)
For integrated circuit (IC) wafer back-end development, state-of-the-art CMOS-technologies have to be developed and robust bond pad structures have to be designed in order to guarantee both functionality and reliability during waferfab processes, packaging, qualification tests, and, of course, usage. It is now well established that for future(More)