Oana Boncalo

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This paper proposes a FPGA implementation based on sliding processing window for Harris corner algorithm. It represents one of the most frequently used pre-processing method, for a wide variety of image processing algorithms, such as feature detection, motion tracking, image registration, etc.. It relies on a series of sequential steps, each processing an(More)
The importance of reliability and fault tolerance is paramount in quantum computation. This paper proposes a Fault Tolerance Algorithms and Methodologies (FTAM) assessment technique for quantum circuits, by adopting the saboteur-based Simulated Fault Injection methodology from classical computation. By drawing the inspiration from classical computation, the(More)
As current microelectronics will reach their physical limits within the foreseeable future, emerging technologies may offer a solution for maintaining the trends to increase computing performance. Biologically-inspired and quantum computing represent two emerging technology vectors for novel computing architectures within nanoelectronics. However, potential(More)
This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMs) designed for quantum systems, by adopting the simulated fault injection methodology from classical computation. Due to their wide spectrum of applications (including quantum circuit simulation) and hierarchical features, the HDLs were employed for(More)
This paper presents gate level delay dependent probabilistic fault models for CMOS circuits operating at sub-threshold and near-threshold supply voltages. A bottom-up approach has been employed: SPICE simulations have been used to derive higher level error models implemented using Verilog HDL. HSPICE Monte-Carlo simulations show that the delay dependent(More)
This paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is based on merging variable and check node processing into one single variable-check node (VCN) unit. Layer message computation is done using a parallel scheme of a number of VCNs equal to the expansion factor of the QC matrix. The proposed(More)