• Publications
  • Influence
Petri Net Analysis Using Boolean Manipulation
This paper presents a novel analysis approach for bounded Petri nets. The net behavior is modeled by boolean functions, thus reducing reasoning about Petri nets to boolean calculation. The stateExpand
  • 186
  • 17
Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets
This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modelingExpand
  • 95
  • 10
Structural methods for the synthesis of speed-independent circuits
Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space thatExpand
  • 27
  • 3
Symbolic Analysis of Bounded Petri Nets
This paper presents a symbolic approach for the analysis of bounded Petri nets. The structure and behavior of the Petri net is symbolically modeled by using Boolean functions, thus reducing reasoningExpand
  • 62
  • 2
Checking signal transition graph implementability by symbolic BDD traversal
This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is theExpand
  • 50
  • 2
Automatic generation of synchronous test patterns for asynchronous circuits
This paper presents a novel approach for automatic test patterngeneration of asynchronous circuits. The techniques used for thispurpose assume that the circuit can only be exercised byExpand
  • 15
  • 1
Structural methods for the synthesis of speed-independent circuits
Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novelExpand
  • 32
  • 1
Checking delay-insensitivity: 10/sup 4/ gates and beyond
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verifying circuits whose behavior isExpand
  • 28
Checking Delay-Insensitivity: 104 Gates and Beyond
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits whose behavior isExpand
  • 26
Hierarchical gate-level verification of speed-independent circuits
This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification timeExpand
  • 21