O. Hashemipour

Publications115
h-index20
Citations1,530
Highly Influential Citations53
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Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology
TLDR
A novel 4x4 bit reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers and can be generalized for NxN bit multiplication.
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits
TLDR
Improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits are demonstrated.
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Design and Evaluation of CNFET-Based Quaternary Circuits
TLDR
These Carbon Nanotube FET-based circuits are compatible with the recent technologies and are designed based on the conventional CMOS architecture, while the previous quaternary designs used methods which are not suitable for nanoelectronics and have become obsolete.
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Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics
This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such…
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Two new low-power Full Adders based on majority-not gates
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High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder
TLDR
This paper presents a high speed Full Adder cell using CNFETs based on majority-not (Minority) function, which shows significant improvement in terms of delay and power-delay product in comparison to contemporary C NFET Adder Cells.
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A 0.6-V, 0.4-µW bulk-driven operational amplifier with rail-to-rail input/output swing
In this paper by using Gm-C compensation technique, an ultra-low-power two-stage operational transconductance amplifier (OTA) with full rail-to-rail input/output swing is presented. The proposed…
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A high-speed current conveyor based current comparator
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An efficient architecture for designing reverse converters based on a general three-moduli set
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CNFET-Based Design of Energy-Efficient Symmetric Three-Input XOR and Full Adder Circuits
TLDR
The simulation results demonstrate the superiority of the proposed structures in terms of speed, power consumption, and power-delay-product compared to other modern CMOS and CNFET-based Full Adder cells.
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