O. Yamamoto

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We propose a neuron-synapse integrated circuit (IC) chip-set for large-scale chaotic neural networks. We use switched-capacitor (SC) circuit techniques to implement a three-internal-state transiently-chaotic neural network model. The SC chaotic neuron chip faithfully reproduces complex chaotic dynamics in real numbers through continuous state variables of(More)
A super parallel embedded processor core (MX core) for SoC (System on Chip) has been developed for multi-media application such as real-time signal processing and image processing. The developed processor realizes high processing performance, small area, low power operation and flexible programmability simultaneously. This paper describes an implementation(More)
Volumetric displays, which directly draw 3D images in the real 3D space, are expected to be used not only in science but also in art. However, most of these displays need complex and expensive optical systems, so they are rarely used in art. In this paper, we propose and describe a volumetric display that has no such optical systems and can be easily(More)
We formalize generating processes of strings based on patterns and substitutions, and give an algorithm to estimate a probability mass function on substitutions, which is an element of processes. Patterns are non-empty sequences of characters and variables. Variables indicate unknown substrings and are replaced with other patterns by substitutions. By(More)
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