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In this paper, a design automation procedure is presented. It is an algorithm driven methodology which is capable of designing and optimizing SI circuits. we applied the proposed methodology to design optimal S21 class AB grounded gate memory cells. Owing to this procedure, this cell designed using the CMOS 0.35pm process under a single 3.3Vpower supply(More)
This article proposes, a reconfigurable FEC system based on Reed-Solomon codec for DVB and WiMax networks. The proposed architecture implements various programmable primitive polynomials. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrical RS-coder-decoder on FPGAs. The implementation, written in a(More)
Motion estimation (ME) is a key operation for video compression. In fact, it contributes heavily to the compression efficiency by removing temporal redundancies. This process is the most critical part in a video encoder and can consume itself more than 50% of coding complexity or computational coding time. To reduce the computational time, many fast ME(More)
The high coding efficiency enabled by the H.264 standard comes with substantially greater algorithmic complexity as compared to that of existing standards. This additional complexity complicates very much the implementation and optimization tasks. However, efficient implementations on different platforms exist that achieve real-time constraints in several(More)
In this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT). Remaining parts were realized in(More)
In this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and distributed arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required(More)
The coding gain of the H.264/AVC video encoder mainly comes from the new incorporated prediction tools. However, their enormous computation and ultrahigh memory bandwidth are the penalties. In this paper we present an approach supporting efficient data reuse process to avoid unnecessary memory accesses and redundant motion estimation computations combined(More)
Contribution à l'élaboration de méthodologies et d'outils d'aide à la conception de systèmes multi-technologiques Soutenance le 27 novembre 2003 devant le jury composé de A mes parents, à mes soeurs, à mon frère, et à mon épouse Houda 3 Ecole Nationale Supérieure des Télécommunications REMERCIEMENTS Le travail présenté dans cette thèse a été effectué au(More)
The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In(More)