Nounchan Panyanouyong

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An implementation of chaotic encoder-decoder on FPGA will be proposed in this paper. Overflow non-linearity by using 2's complement number in digital filter causes the phenomenon called "Chaos" in digital filter. An 1ER filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. Filter coefficients of both encoder and decoder can(More)
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