Norman Chang

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With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to IR-drop, L di/dt noise, or LC resonance. Therefore, Power-Ground(More)
A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg) for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from(More)
In this paper, we present an efficient yet accurate inductance extraction methodology and its application to clocktree RLC extraction. We first show that without loss of accuracy, the extraction problem of n traces with or without ground planes can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace(More)
Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more concerned with the step power reduction instead of the average power reduction. The step power is defined as the power difference between the previous and present clock cycles,(More)