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In this paper, we present an efficient yet accurate inductance extraction methodology. We first show that without loss of accuracy, the extraction problem of n traces can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace subproblems via a table-based approach. The table-based inductance model has been(More)
On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire(More)
With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to IR-drop, L di/dt noise, or LC resonance. Therefore, Power-Ground(More)
A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg) for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from(More)
In this paper, we develop a 2"d order distributed RLC waveform model that captures both delay and overshoot effects more accurately than previous 1'' order models. We then present a new approach to decoupling a set of coupled RLC lines by examining current return paths. Noise and delay results from this technique match SPICE for a wide range of input(More)
In this paper, we present an efficient yet accurate inductance extraction methodology and its application to clocktree RLC extraction. We first show that without loss of accuracy, the extraction problem of n traces with or without ground planes can be reduced to a number of one-trace and two-trace subproblems. We then solve one-trace and two-trace(More)