Norman Chang

Learn More
With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to IR-drop, L di/dt noise, or LC resonance. Therefore, Power-Ground(More)
A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg) for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from(More)
In this paper, we present an efficient yet accurate inductance extraction methodology and its application to clocktree RLC extraction. We first show that without loss of accuracy, the extraction problem of n traces with or without ground planes can be reduced to a number of one-trace and twotrace subproblems. We then solve one-trace and twotrace subproblems(More)
An efficient layout-based multi-domain ESD analysis and verification method has been developed for large SoC designs containing thousands of bumps. A fast resistance and current density check for ESD discharging paths across multiple diodes/clamps represented as I-V curves is performed, including on-chip signal/power/ground/package grid. Real application(More)
Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology and its applications to accurately and(More)
Federating the portability and mobility of mobile devices with the computation capacity on desktop computers have been a widely discussed computation model for the next decade. However, the mobility of the mobile devices also introduces challenges on the federation. This work developed the elastic computation framework to tackle the aforementioned(More)
On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire(More)
A multilayer, full chip thermal analysis is presented. The design of the chip at functional-block level is directly captured to the simulator, allowing the assessment of the chip layout impact on the system performance due to the elevated operational temperature. The heat generation for each block is obtained by running the circuit-level electrical(More)