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Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) Accurate soft error(More)
This paper presents an overview of the Built-In Soft Error Resilience (BISER) technique for correcting soft errors in latches, flip-flops and combinational logic. The BISER technique enables more than an order of magnitude reduction in chip-level soft error rate with minimal area impact, 7-11% chip-level power impact, and 1-5% performance impact (depending(More)
OBJECTIVE This study investigated the relationship between outcome and structural brain abnormalities in schizophrenia. METHOD Intracranial volume and volumes of the cerebrum, gray and white matter, lateral and third ventricles, frontal lobes, thalamus, and cerebellum were measured in 20 patients with a poor outcome, 25 with a favorable outcome, and 23(More)
In this paper, we introduce an approach for computing soft error susceptibility of nodes in large CMOS circuits at the transistor level. The node sensitivity depends on the electrical, logic, and timing masking. An efficient technique is developed to compute the electrical masking of nodes from the characterization tables and the inverse pulse propagation.(More)
  • C Bormann, J Ott, H.-C Gehrck, T Kerschat, N Seifert
  • 1994
Existing reliable multicast transport protocols have focused on achieving reliability from the point of view of senders of messages. Many applications in the area of synchronous groupware do not need this strong property, but can nonetheless benefit from a reliable multicast protocol. For use with the X window sharing tool Xy, we hav e implemented the(More)