Noppanunt Utamaphethai

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In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper focuses on the reduction of load instruction execution latency. Load execution latency is dependent on memory access latency, pipeline depth, and data dependencies. Through load(More)
We describe a rigorous ATPG-like methodology for validating the branch prediction mechanism of the PowerPC604 which can be easily generalized and made applicable to other processors. Test sequences based on nite state machine (FSM) testing are derived from small FSM-like models of the branch prediction mechanism. These sequences are translated into PowerPC(More)
We propose a methodology for validating microarchitecture specifications. We view microarchitecture features as specific operations on entries of various buffers in the processor. Our validation approach is to determine the functionality of a buffer type, model its operations at the microarchitecture level using abstract finite state machine (FSM) models,(More)
Microprocessor performance has been doubling every eighteen months for nearly two decades. Improvements in the semiconductor manufacturing process, the use of deeper pipelines and aggressive microarchitecture mechanisms are among the most important factors in such an impressive increase. But higher performance also comes with an increased cost. Signi cant(More)
Microprocessor designers use multiple simulation tools with varying degrees of modeling details ranging from the instruction set of the microprocessor to the circuit implementation. Here, we focus on tool design for the development of microarchitectures, which implement the instruction set. Microarchitecture design involves both functional and performance(More)
In this paper, we evaluate the eeectiveness of the buuer-oriented microarchitecture validation methodology 1, 4, 5]. A list of design faults suggested by our industrial collaborator 2, 3] is used and investigated to determine if they can be detected by our generated validation sequences. Two metrics are used to determine the detection of the design faults:(More)