Nobukazu Takai

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This paper describes techniques for creating a lowpower SAR ADC with an error-correcting non-binary successive approximation algorithm; it is suitable for low power applications, performs digital error correction, and does not require analog calibration. Two techniques have been proposed for implementing low-power SAR ADCs: use of two comparators, and a(More)
This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable. key(More)
This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors can be(More)
This paper describes an algorithm for Successive Approximation Register (SAR) ADCs with overlapping steps that allow comparison decision errors (due to, such as DAC incomplete settling) to be digitally corrected. We generalize this non-binary search algorithm, and clarify which decision errors it can digitally correct. This algorithm requires more SAR ADC(More)
This paper describes a time-to-digital converter (TDC) architecture with fine time resolution, self-calibration and self-testing, and these features are realized by the following: (1) Encoder circuit that ensures monotonic characteristics. (2) Self-calibration circuit for linearity improvement. (3) Stochastic architecture for fine time resolution. (4)(More)
This paper proposes an improved method of background calibration that reduces production testing time of mixedsignal ICs. Production testing time typically consists of “calibration convergence time” + “functional testing time after calibration convergence”. The method that is proposed here reduces average calibration convergence time. This method does not(More)
This paper describes an algorithm for generating test signals to efficiently test the linearity of ADCs. Linearity is an important testing item for ADCs, and it takes a long time (hence is costly) to test low-sampling-rate, high-resolution ADCs. We here propose to generate a test signal consisting of multiple sine waves, to precisely test the linearity for(More)
This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors can be(More)
This paper describes a bipolar outputs DC-DC converter that uses a single inductor for size and cost reduction. We propose timing diagram for a charge pump circuit in the negative voltage generation part, and present its configuration, operation principle and simulation results. We also show that employing pseudo-continuous conduction mode improves(More)
This paper proposes spread-spectrum clock modulation algorithms for EMI reduction in digitally-controlled DC-DC converters. In switching regulators using PWM, switching noise and harmonic noise concentrated in a narrow spectrum around the switching frequency can cause severe EMI. Spread-spectrum clock modulation can be used to minimize EMI. In conventional(More)