Nitin Anand

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This work presents a new single-port 6T SRAM cell with a single-ended read operation (read-decoupled) and shows significant improvement in read stability and write-ability as compared to the conventional 6T (CON6T) SRAM cell. Unlike the CON6T cell where the pull-up transistors are powered by the supply voltage (VDD), the proposed cell has powered these(More)
This article presents a highly stable single-ended 7T (SE-7T) SRAM cell in subthreshold region. Using Monte-Carlo simulations critical design metrics of proposed SE-7T SRAM cells are estimated. Estimated results are compared with that of conventional 6T SRAM cell. The SE-7T SRAM cell offers 2.71× and 2.71× and 8.42 X improvements in Read(More)
This article presents a variability resilient CNFET based 10T S RAM cell. Critical design metrics of S RAM cells are estimated using Monte-Carlo simulations and compared with that of conventional Si-MOSFET based 10T S RAM cell. The CNFET based SRAM cell offers 3.15&#x00D7; and 1.98&#x00D7; improvements in Read Access Time (T<sub>RA</sub>) and Write Access(More)
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