Nirav H. Dave

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—CHERI extends a conventional RISC Instruction-Set Architecture, compiler, and operating system to support fine-grained, capability-based memory protection to mitigate memory-related vulnerabilities in C-language TCBs. We describe how CHERI capabilities can also underpin a hardware-software object-capability model for application compartmentalization that(More)
In this thesis, we designed a 2-way out-of-order processor in Bluespec implementing the MIPS I integer ISA. A number of scheduling optimizations were then used to bring the initial design up to the same level of cycle-level concurrency as found in standard RTL-level designs. From this, a general design methodology is proposed to effectively express, debug,(More)
Previous research on consistent updates for distributed network configurations has focused on solutions for centralized network-configuration controllers. However, such work does not address the complexity of modern switch datapaths. Modern commodity switches expose opaque configuration mechanisms, with minimal guarantees for datapath consistency and with(More)
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