Ninghan Zheng

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Helper threaded prefetching based on Chip Multiprocessor is a well known approach to reducing memory latency and has been explored in linked data structures accesses. However, conventional helper threaded prefetching often suffers from useless prefetches and cache thrashing, which affect its effectiveness. In this paper, we first analyzed the shortcomings(More)
Helper threaded prefetching based on chip multiprocessor has been shown to reduce memory latency and improve overall system performance, and has been explored in linked data structures accesses. In our earlier work, we had proposed an effective threaded prefetching technique that balances delinquent loads between main thread and helper thread to improve(More)
Helper thread prefetching can improve performance of irregular data-intensive applications. However, helper thread prefetching quality depends on the values of control parameters. Adopting traditional manual methods to find the better values of control parameters is a time-consuming and complicated enumeration process. For selecting dynamically the better(More)
At our university, since the Spring of 2005, we have been teaching a first course about data cache on CMP from computer architecture. We have accomplished several goals. The most important of which is the analysis and experimental approach for pull-based data prefetching and push-based data prefetching on CMP. The pedagogical style embodied in this course(More)
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