Niloofar Razavi

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We propose null-pointer dereferences as a target for finding bugs in concurrent programs using testing. A null-pointer dereference prediction engine observes an execution of a concurrent program under test and predicts alternate interleavings that are likely to cause null-pointer dereferences. Though accurate scalable prediction is intractable, we provide a(More)
In this paper, we describe (con)2colic testing - a systematic testing approach for concurrent software. Based on concrete and symbolic executions of a concurrent program, (con)2colic testing derives inputs and schedules such that the execution space of the program under investigation is systematically explored. We introduce interference scenarios as key(More)
SystemC is a system-level modeling language that can be used effectively for hardware/software co-design. Since a major goal of SystemC is to enable verification at higher levels of abstraction, the tendency is now directing to introducing formal verification approaches for SystemC. In this article, we propose an approach for formal verification of SystemC(More)
In this paper, we introduce a component-based approach to specify and verify system-level designs. A coordination language, Reo, is used to support hierarchical design and verification. We move from functional specification to implementation through different levels of abstraction, considering TLM/RTL mixed levels and hardware/software co-designs. We(More)
SystemC is a system level modeling language with the goal of enabling verification at higher levels of abstraction. In this paper, we propose a mapping from SystemC designs to Rebeca models supported by an automatic tool, Sytra. Rebeca verification tool set is then available for verifying LTL and CTL properties. The mapping is aimed to preserve the(More)
Testing concurrent programs is a challenging problem due to interleaving explosion: even for a fixed set of inputs, there is a huge number of concurrent runs that need to be tested to account for scheduler behavior. Testing all possible schedules is not practical. Consequently, most effective testing algorithms only test a select subset of runs. For(More)
In this paper, we propose a component-based approach to verify system-level designs. The coordination language Reo is selected as an Architecture Description Language (ADL) to model system designs written in SystemC. In our approach we map a SystemC design to a Reo circuit, and then construct the corresponding constraint automata which show the behavior of(More)
Testing concurrent programs is a challenging problem: (1) the tester has to come up with a set of input values that may trigger a bug, and (2) even with a bug-triggering input value, there may be a large number of interleavings that need to be explored. This paper proposes an approach for testing concurrent programs that explores both input and interleaving(More)
Testing concurrent programs is more difficult than testing sequential programs due to the interleaving explosion problem: even for a fixed program input, there are numerous different runs that need to be tested to account for scheduler behaviour. Testing all such interleavings is not practical. Consequently, most effective testing algorithms attempt to(More)