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Scaling towards kilo-core processors with asymmetric high-radix topologies
In this paper, we explore the challenges in scaling on-chip networks towards kilo-core processors. Current low-radix topologies optimize for fast local communication, but do not scale well toExpand
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Checkpointing Exascale Memory Systems with Existing Memory Technologies
Building exascale supercomputers requires resilience to failing components such as processor, memory, storage, and network devices. Checkpoint/restart is a key ingredient in attaining resilience, butExpand
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Enhancing DRAM Self-Refresh for Idle Power Reduction
DRAM can enter self-refresh mode to save power during idle periods. But self-refresh mode does not modify or reduce the number of refresh operations, therefore the refresh energy stays the same. WeExpand
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Quality-of-service for a high-radix switch
Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessaryExpand
Low Design-Risk Checkpointing Storage Solution for Exascale Supercomputers
This work presents a checkpointing solution for exascale supercomputers that employs commodity DRAM and SSD devices that pose a low design risk compared to solutions that use emerging non-volatileExpand
SMART: STT-MRAM architecture for smart activation and sensing
STT-MRAM is a promising drop-in replacement for DRAM for main memory, because it can offer higher energy efficiency than DRAM with comparable latency. Implementing STT-MRAM similar to traditionalExpand