- Full text PDF available (27)
- This year (1)
- Last 5 years (30)
- Last 10 years (55)
Journals and Conferences
This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG… (More)
This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of m& reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented.
A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based System-On-Chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific Test Access Mechanism… (More)
A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis.
<para> Unknown (X) states are increasingly often identified as having potential for rendering semiconductor tests useless. One of the key requirements for a reliable test response compactor is, therefore, to preserve observability of any scan cell for a wide range of X-profiles while maintaining very high-compaction ratios, providing ability to detect a… (More)
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quality. The System-onChip (SoC) design flow and the changes necessary to successfully implement EDT are presented. Experimental results for three SoC designs targeted for automotive,… (More)
The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one onchip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much