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This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG… (More)
This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture , the compression algorithm, design flow, experimental results, and silicon implementation are presented.
The paper presents a two-stage test response compactor with an overdrive section and scan chain selection logic. The proposed solution is capable of handling a wide range of X state profiles, offers compaction much higher than the ratio of scan chains to compactor outputs, and provides excellent diagnostic resolution 1. Introduction Test response… (More)