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—This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the storage element to the clock distribution network. The(More)
A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower Energy-Delay Product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using(More)
Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve Energy-Delay Product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. This property makes conditional methods(More)
—This paper represents a departure from the conventional methods of design and analysis of clocked storage elements that rely on minimizing a fixed energy–delay metric. Instead it establishes a systematic comparison in the energy–delay design space based on the parameters of the surrounding blocks. We define the composite energy-efficient characteristic(More)
A new Skew Tolerant Flip-Flop (STFF) that achieves the lowest reported delay and energy-delay product while absorbing up to 54ps of clock skew is described. In addition, a method for characterizing clock skew absorbing flip-flops is presented. This comparison is apples-to-apples because the best previously reported flip-flops [1-4] are fabricated on the(More)
—We present a method, on-chip test circuitry, and an error analysis, for accurate measurement of timing characteristics and power consumption of clocked storage elements. The test circuit was fabricated in 0.11 m CMOS technology and the measurements performed automatically using a serial scan interface. The precision and accuracy of the presented method are(More)
A dual-edge triggered flip-flop suitable for low power applications is presented. HSPICE simulations conducted in 0.11u CMOS technology using 1.2V power supply voltage show that the proposed design is comparable in energy-delay product to high-performance single-edge triggered flip-flops while maintaining lower clock power. The Energy-Delay Product(More)