A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower Energy-Delay Product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using… (More)
—This paper describes the classification, detailed timing characterization, evaluation, and design of the dual-edge triggered storage elements (DETSE). The performance and power characterization of DETSE includes the effect of clocking at halved clock frequency and impact of load imposed by the storage element to the clock distribution network. The… (More)
An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the t pLH and t pHL of the flip-flop and careful design of keeper elements in the circuit. New design… (More)
A novel timing characterization for dual-edge triggered flip-flops is presented in this paper. This characterization takes into account the real overhead taken from the clock cycle by the flip-flops. Our study shows the correctness of this new metrics when compared against data-to-output delay.
In this paper we present the effect of process variations on the design of clocked storage elements. This work proposes to use the Energy-Delay space analysis for a true representation of the design trade-offs. Consequently, this work also shows a comparison of clocked storage elements under a specific set of system constraints for typical corner design and… (More)
—In this paper, we analyze the occurrence of jitter due to random and deterministic disturbances in nonautonomous current mode logic circuits. First, we present an analytical model that explains the transformation of noise into jitter as a linear time-variant process, with its time-domain impulse response function and a frequency-domain system function. The… (More)
A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as a linear time-varying (LTV) process, as opposed to a previously published method, which models jitter generation as a linear time-invariant (LTI) process. Predictions obtained… (More)