Niklas Lotze

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The design of sub-threshold circuits is especially challenging due to the massive impact of process variations. These variabilities also heavily affect circuit timing, a problem only considered concerning combinational gates so far. In this paper the effects of process variations on flip-flop timing at sub-threshold voltages are analyzed based on extensive(More)
Despite an increasing interest in digital sub-threshold circuits little research has been dedicated to timing modeling in this voltage domain so far. Especially high timing variabilities makes proper modeling necessary to allow for the prediction of timing behavior and timing yield on the path towards design automation. This paper first deals with gate(More)
This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled circuits face these difficulties with self-timed operation(More)
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