Niklas Lotze

Learn More
The design of sub-threshold circuits is especially challenging due to the massive impact of process variations. These variabilities also heavily affect circuit timing, a problem only considered concerning combinational gates so far. In this paper the effects of process variations on flip-flop timing at sub-threshold voltages are analyzed based on extensive(More)
Despite an increasing interest in digital sub-threshold circuits little research has been dedicated to timing modeling in this voltage domain so far. Especially high timing variabilities makes proper modeling necessary to allow for the prediction of timing behavior and timing yield on the path towards design automation. This paper first deals with gate(More)
This paper investigates self-timed asynchronous design techniques for subthreshold digital circuits. In this voltage range extremely high voltage-dependent delay uncertainties arise which make the use of synchronous circuits rather inefficient or their reliability doubtful. Delay-line controlled circuits face these difficulties with self-timed operation(More)
This paper introduces a state-of-the-art design of a high speed sigma delta digital to analog converter (DAC), which can be integrated into a system-on-a-chip (SOC) for different communication transceivers. The operation speed in the digital circuit is very important for accomplishing the performance which can satisfy different communication protocol(More)
This paper introduces an improved method for pulse shaping filtering in a digital communication modulator. This method uses memory to store different waveform frames instead of the FIR filter coefficients. At the run time, the interpolation for pulse shaping can be directly done by retrieving these waveforms from the memory without any arithmetic operations(More)
A power-efficient narrow-band tunable digital front end (DFE) for bandpass sigma–delta (ΣΔ) analog-to-digital converters is presented. The proposed architecture introduces a new system topology, splitting the down converter into two mixers and placing a cascaded integrator-comb decimation stage between the two mixers. The first mixer is a quadrature mixer(More)
  • 1