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The auditory system in humans and animals makes virtually no discrimination of phase changes in the structure of monaurally presented sound signals. However, electrophysiological studies have demonstrated marked changes in the responses of the central parts of the auditory system when the phase structure of the signal changes during presentation of the same(More)
The aim of the present study is to test whether mismatch negativity (MMN) response can be elicited by changes in auditory motion dynamics. The discrimination of auditory motion patterns was investigated using psychophysical and electrophysiological methods in the same group of subjects. Auditory event-related potentials (ERP) were recorded for stationary(More)
In experiments on anaesthetized cats, studies have been made of intracellular and extracellular responses of single units in the auditory cortex during dichotic stimulation simulating sound source motion. Responses of some cortical units exhibit strong dependence on the signal parameters related to spatial and directional characteristics of simulated sound(More)
The spike responses of individual neurons in the primary auditory cortex were studied in anesthetized cats during exposure to stationary and moving stimuli with static or dynamically changing interaural delays (deltaT). Static stimuli were tones and clicks. Dynamic stimuli were created using series of synphase and antiphase clicks with interaural delays(More)
Lateralization of moving fused auditory images (FAIs) was studied under dichotic stimulation, with FAI movement from the right and left ears to midline. The movement was produced by the gradual change of interaural time delay (from +/- 630 to 0 microseconds) in a binaurally presented click train in which a constant interaural intensity difference (IID)(More)
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provide fast analytical models to estimate average performance. This paper presents a new analytical model that focuses on QoS assurance. It assumes that the NoC has an underlying(More)
—The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more hierarchical structures to better exploit locality. During the exploration and design of CMP architectures, it is essential to efficiently(More)
—The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and the message routes for the traffic among the processing elements of the system. The solution of the(More)
The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping onto general-purpose CMPs with multiple pre-defined voltage islands for power management. The CMPs are assumed to contain different classes(More)