Nikhil P. Rahagude

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While scan-based testing achieves a high fault coverage, it requires long test application times and substantial tester memory, in addition to the overhead in chip area and high test power. Functional testing, on the other hand, suffers from low coverage but can be applied at-speed. In this paper, we propose a novel three-step design-for-test (DFT)(More)
(ABSTRACT) While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid silicon diagnosis. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently(More)
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