Nihar Ranjan Mohapatra

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Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time.(More)
In this paper, the performance of Zero capacitor RAM (Z-RAM<inf>&#x00AE;</inf>) devices, developed in a 45nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes. It is shown that the asymmetrically doped Z-RAM (AD) devices offer much better memory performance compared to the symmetrically doped Z-RAM (SD) devices.
With advancement in technology, there is an increase in the size of current files, thus leading to a demand in increase in data transfer rate. Line encoding can potentially help in increasing speeds by dramatically reducing overheads without necessitating improvements in SERDES devices. Conventionally this technique is suited for optical fiber communication(More)
Practical models of lithographic processes are usually empirically calibrated, making their accuracy dependent on the total number of samples used to build the models, and more specifically on the selection of a representative set of samples for calibration. An inadequate number of samples can adversely impact model accuracy, but a broadly comprehensive set(More)
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