Nicolas Sillon

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Through Silicon Via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more(More)
This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV(More)
Through Silicon Via (TSV) is a very attractive solution for 3D stacking. Currently the main technique in industrial TSV processes is the via-last approach. But the via-first approach has also many advantages and in particular allows the use of high thermal budget materials for high voltage applications. In this work, we will show results on process(More)
3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customer’s interest by showing him(More)
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