Nicholas J. Stessman

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{ Analog IC test occupies a signicant fraction of the design cycle. Testing costs are increased by the twin requirements of high precision and accuracy in signal measurement. We discuss a system level ACOB technique for fully dierential analog ICs. Our test techniques incorporate analog specic constraints such as device matching, and circuit and switching(More)
We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without aaecting fault coverage. Our methods can be(More)
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