A systematic general rounding procedure is proposed for oating-point arithmetic operations. This procedure consists of 2 steps: constructing a rounding table and selecting a prediction scheme. Optimization guidelines are given in each step to allow hardware to be minimized. This procedure-based rounding method has the additional advantage that veriication… (More)
Utility can be defined as quality per unit of cost. The utility of a particular function in a microprocessor can be defined as its contribution to the overall processor performance per unit of implementation cost. In the case of on-chip data memory (e.g., registers, caches) the performance contribution can be reduced to its effectiveness in reducing memory… (More)
This paper presents the concept of leading-one prediction (LOP) used in most high-speed floating-point adders in greater detail and describes two existing implementations. The first one is similar to that used in the TBM RS /GO00 processor. The second is a distributed version of the first, consuming less hardware when multiple patterns need to be detected.… (More)
This paper describes the design and implementation of the oating-point adder in the Stanford Nanosecond Arithmetic Processor (SNAP). The adder is capable of adding two double precision IEEE numbers in less than 20ns nominal with all IEEE rounding modes. Only round to nearest is described in this paper, however. The adder has been laid out in the HP CMOS26… (More)
This paper describes an improved, IEEE conforming oating-point addition algorithm. This algorithm has only one addition step involving the signiicand in the worst-case path, hence ooering a considerable speed advantage over the existing algorithms, which t ypically require two to three addition steps.
The increasing computation requirements of modern computer applications have stimulated a large interest in developing extremely high-performance floating-point dividers. A variety of division algorithms are available, with SRT being utilized in many computer systems. A careful analysis of SRT divider topologies has demonstrated that a relatively simple… (More)
SNAP — the Stanford subnanosecond arithmetic processor — is an interdisciplinary effort to develop theory, tools, and technology for realizing an arithmetic processor with execution rates under 1 ns. Specific improvements in clock-ing methods, floating-point addition algorithms, floating-point multiplication algorithms, division and higher-level function… (More)
a dissertation submitted to the department of electrical engineering and the committee on graduate studies of stanford university in partial fulfillment of the requirements for the degree of doctor of philosophy ii I certify that I have read this dissertation and that in my opinion it is fully adequate, in scope and in quality, as a dissertation for the… (More)