Nelson Acosta

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High-speed digital designs exhibit a moderate logic depth, gate count, and wiring capacitance. These three characteristics are also essential conditions for a low-power operation. Therefore, blocks with lower area or higher bandwidth can be good candidates to have a moderated power figure. This fact opens a way to overcome the lack of low-power EDA tools(More)
— The accuracy of a standard market receiver GPS (Global Positioning System) is near 10-15 meters the 95% of the times. To reach a sub-metric level of accuracy some techniques must be used [1]. This article describes some of these procedures to improve the positioning accuracy by using a low-cost GPS in a differential relative positioning way. The proposed(More)
In this paper a compiler capable of generate Multiple Instruction Single Data (MISD) architectures for feature vector calculation is presented. The input is a high-level language, avoiding to developers to involve in low level design. Instead, the output is expressed in a Hardware Description Language (HDL), and can be used for FPGA configuration. A FPGA is(More)
Resumen En este trabajo se muestra la conexión entre la profundidad de lógica y el determinismo de las herramientas de emplazamiento y rutado. La idea se verifica mediante una serie de experimentos utilizando herramientas y silicio del fabricante de FPGAs Xilinx. Abstract In this work, a relationship between logic depth and the determinism of the place and(More)
Resumen: En este artículo se presenta una herramienta para el análisis de la interconexión de circuitos mapeados en FPGAs. A partir de los ficheros de información post-layout, el programa permite seleccionar subconjuntos de pistas de un determinado fanout, graficar histogramas de retardos, calcular estadísticas, analizar skew de reloj, o exportar esta(More)