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Genetically hard-wired neural mechanisms must enforce behavioral reproductive isolation because interspecies courtship is rare even in sexually naïve animals of most species. We find that the chemoreceptor Gr32a inhibits male D. melanogaster from courting diverse fruit fly species. Gr32a recognizes nonvolatile aversive cues present on these reproductively(More)
Systems from smartphones to supercomputers are increasingly heterogeneous, being composed of both CPUs and GPUs. To maximize cost and energy efficiency, these systems will increasingly use globally-addressable heterogeneous memory systems, making choices about memory page placement critical to performance. In this work we show that current page placement(More)
Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power, and it is key to capture the complex behaviour of the DRAM controller when evaluating(More)
Historically, GPU-based HPC applications have had a substantial memory bandwidth advantage over CPU-based workloads due to using GDDR rather than DDR memory. However, past GPUs required a restricted programming model where application data was allocated up front and explicitly copied into GPU memory before launching a GPU kernel by the programmer. Recently,(More)
BACKGROUND Tuberculous meningitis (TBM) is a major global health problem, and it is sometimes difficult to perform a differential diagnosis of this disease from other diseases, particularly partially-treated pyogenic meningitis (PTPM). In an earlier study, we demonstrated the presence of a 30-kD protein antigen in cerebrospinal fluid (CSF) of TBM patients.(More)
For the sentence boundary detection task, we applied a Maximum Entropy (MaxEnt) classifier using several different features based on the local context. We compared the performance of training our classifier on the Wall Street Journal (WSJ) corpus and testing on three data sets: the WSJ and Brown Penn Treebank corpora and the GENIA corpus. Our results(More)
Cache coherence is ubiquitous in shared memory multiprocessors because it provides a simple, high performance memory abstraction to programmers. Recent work suggests extending hardware cache coherence between CPUs and GPUs to help support programming models with tightly coordinated sharing between CPU and GPU threads. However, implementing hardware cache(More)
Application of logical effort on transistor-level analysis of different adder architecture is presented. Logical effort method is used to estimate delay and impact of different adder topologies. The tested adder topologies were 8-bit Carry skip adder and 4bit ripple carry adder. The efficiency of the model is analyzed by circuit simulation using TSPICE for(More)