Ne Kyaw Zwa Lwin

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We propose an dynamic-voltage-scaling (DVS) non-imprinting Master-Slave SRAM with high speed erase, for low power high secured defense applications. There are three key features in the proposed design. First, the stored data is periodically toggling in the SRAM cell to prevent data imprint, hence our design is highly secured against the unauthorized attack.(More)
We propose an 18-bit 5-interface asynchronouslogic Network-on-Chip (ANoC) router based on the quasi-delayinsensitive (QDI) realization approach for high secured cryptography applications. There are four key features of the proposed ANoC router. First, it embodies the novel high-speed low-power Sense-Amplifier Half Buffer 4-rail cells. Second, it is designed(More)
We propose a Success Rate (SR) estimation model for Correlation Power Analysis (CPA) attack on AES-128 encrypted devices. The SR is a ratio between the number of successful attacks to obtain secret key and the total number of attacks. There are two key features in the proposed model. First, we derive the Second Order Standard Deviation (SOSD) of the(More)
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