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Importance of addressing soft errors in both safety critical applications and commercial consumer products is increasing, mainly due to ever shrinking geometries, higher-density circuits, and employment of power-saving techniques such as voltage scaling and component shut-down. As a result, it is becoming necessary to treat reliability as a first-class(More)
Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulation for reliability-oriented high-level synthesis that addresses the soft error problem. The proposed approach tries to maximize reliability of the design while observing the bounds(More)
This paper proposes a reliability-centric hardware/ software co-design framework. This framework operates with a component library that provides multiple alternates for a given task, each of which is potentially different from the others in terms of reliability, performance, and area metrics. The paper also presents an experimental evaluation of the(More)
In this paper a methodology based on Ant colony optimization is presented to generate optimal scheduling during high-level synthesis. The classical force equation of the Force-directed scheduling algorithm has been modified to accommodate the experiences accumulated by multiple agents in different iterations. In each iteration the obtained schedule is(More)
The state space explosion problem is a hurdle in the acceptance of model checking as a viable tool for verification of large-scale designs. Abstractions may be used to simplify designs, while preserving target verification properties. We propose a simple methodology for abstracting away portions of the data path, thus rendering a large state-space model of(More)
With the migration to deep sub-micron process technologies, the power consumption of a circuit has come to the forefront of concerns, and as a result, the power has become a critical design parameter. This paper presents a novel high-level synthesis methodology, called Power Islands Synthesis, that eliminates the spurious switching activity and the leakage(More)
We present a methodology for formal verification of scheduling phase of High-Level Synthesis (HLS) when speculative code motions are performed during this process. Verification relies on establishing functional equivalence between the result of scheduling and the behavioral specification of the design, using their FSMD models. We propose and formally define(More)
With the migration to Deep Sub-Micron (DSM) process technologies, the static power (leakage) has become the major contributor to the design's overall power consumption. In this work, we will show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We will also present a novel(More)