Navid Toosizadeh

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The method presented in this paper is mostly based on recognition using vertical and horizontal projections of Persian digits, along with other characteristics of them. The presented method makes recognition of Persian digits fast with 0% error. Since, at this stage the main goal is designing an algorithm suitable for hardware implementation, a single size(More)
Synchronous pipelines usually have a fixed clock frequency determined by the worst-case process-voltage-temperature (PVT) analysis of the most critical path. Higher operating frequencies are possible under typical PVT conditions, especially when the most critical path is not triggered. This paper introduces a design methodology that uses asynchronous design(More)
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable(More)
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