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The VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early as possible. In this paper, we propose a method to combine interconnect planning(More)
A new approach to the interconnect-driven floorplanning problem that integrates bus planning with floorplanning is presented. The integrated floorplanner is intended for bus-based designs. Each bus consists of a large number of wires. The floorplanner ensures routability by generating the exact location and shape of interconnects (above and between the(More)
Given a number of routing layers, the multilayer topological planar routing problem is to choose a maximum (weighted) set of nets so that each net in the set can be topologically routed entirely in one of the given layers without crossing other nets. This problem has important application in the layout design of multilayer IC technology, which has become(More)
The hypercube, though a popular and versatile architecture, has a major drawback in that its size must be a power of two. In order to alleviate this drawback, Katsee Kat88] deened the Incomplete Hypercube, which allows a hypercube-like architecture to be deened for any number of nodes. In this paper we generalize this deenition and introduce the name(More)
In this paper, we present a new three layer OTC channel routing algorithm for high performance circuits. This router not only minimizes the channel height by using OTC areas but also minimizes the net lengths. Our algorithm is novel in two respects, one, we compute the track bound for each net and the other is that we use 45° segments for routing. We have(More)
A new channel segmentation model for high performance FPGAs is presented. In this model! a channel is partitioned into several regionsand each region consists of trach of equal length segments: but segment length is varied uniformly across the rcgrons. Each IV-gion is allocated certain number of tracks, however the segments are not arranged in an uniform(More)
This paper presents three minimum-area floorplanning algorithms that use flexible arbitrary rectilinear shapes for the standard cell regions in MBC design. The first algorithm (pure HCST) introduces a grid traversal technique which guarantees a minimum-area floorplan. The second algorithm (Hybrid-BF) uses a combination of HCST and Breadth First (BF)(More)