Nauman H. Khan

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3-D integrated circuits promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, renders the design of 3-D power delivery a challenge. We investigate in this paper various methods to improve 3-D power delivery. We analyze the impact of through-silicon via (TSV) size and(More)
http://www.itrs.net/Links/2008ITRS/Home2008.htm Abstract—Three-dimensional integrated circuits (IC) promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, render 3D power delivery design a challenge. In this paper, we provide a system-level comparison of power delivery(More)
Through-Silicon Via (TSV) is a critical interconnect element in 3D integration technology. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical design and process parameters including(More)
Through-silicon vias (TSVs) in 3-D ICs are a major source of substrate noise, causing performance degradation of neighboring active devices. To reduce this noise, we propose using a tungsten-filled ground plug, a TSV-like structure that connects to ground (GND) and that partially or completely extends through the substrate. We evaluate the impact of plug(More)
Through-Silicon Via (TSV) is a critical interconnect element in 3D integration technology. TSVs introduce many new design challenges. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical(More)
To harness the full potential of 3-D integrated circuits, analysis tools for early design space exploration are needed. Such tools, targeting multiple design facets and cost trade-off analysis, would allow designers to arrive at major decisions regarding architecture and implementations fabrics. We focus in this paper on the efficient estimation of on-chip(More)
It's not surprisingly when entering this site to get the book. One of the popular books now is the designing tsvs for 3d integrated circuits. You may be confused because you can't find the book in the book store around your city. Commonly, the popular book will be sold quickly. And when you have found the store to buy the book, it will be so hurt when you(More)
Increased power density and package asymmetry pose challenges in designing power delivery networks for 3-D Integrated Circuits (ICs). The increased resistivity of Cu wires due to scaling has shifted attention to alternate interconnect technologies. Continued and significant innovations in CNT manufacturing at CMOS-compatible temperatures with quality(More)
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