This paper introduces a denotational semantics for a core of the draft IEEE standard analog and mixed signal design language VHDL-AMS, and derives general results about the behaviour of VHDL-AMS programs from it. We include, for example, a demonstration that VHDL-AMS par-allelism is benign in the absence of shared initializations. As proof of concept we… (More)
The application and development of reusable components (Intellectual Property, IP) has become a regular part of modern design practices. The IP provider on the one hand side and the IP integrator (user) on the other side may be in the same company or separate participants in the microelectronic design market. In both cases, the transfer of IP remains a… (More)
This paper presents a methodology for hardware-software co-design. It is based on the formal description technique LOTOS in the specification phase, and on estimation methods at different levels of abstraction in the partitioning phase. The LOTOS specification describes the system as a set of interacting communicating processes. Our HW-SW partitioning… (More)
Several European research projects in the vehicular area address the enhancement of vehicular safety. In the frame of the Caring Cars project, an on-board car-gateway embedded architecture for safety and wellness applications has been designed. This paper puts forward the essentials of this modular, dynamic and robust architecture and defines in detail the… (More)
Currently, several multimedia devices support the UPnP protocol allowing automatic detection of devices, connection of devices and agreement on a certain quality of the communication established between a server of content (Media Server) and a player of content (Media Renderer). The focus of this paper is to add to the UPnP standard quality of service (QoS)… (More)
– Reuse of semiconductor IP modules is widely perceived as a means to overcome the design gap , enabling the development of complex systems-on-chip under narrow manpower and time-to-market constraints. However, for the IP business to be a success, many requirements related to the portability, maintainability, and quality of an IP module must be met. This… (More)
A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is “correct by construction”. the calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general.… (More)
The application of design reuse to analog and mixed-signal components for System-on-Chip (SoC) is an emerging and revolutionary field. This paper presents a methodological approach to this area illustrated with a mixed-signal case study.