Nathan Schemm

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This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel processing. In the architecture, an 8-b RISC processing core is embedded in an 8×8 array of digital pixel sensors on the same focal plane. These neighborhood processors (NPs) are tiled in a 2-D array to form the final imager resolution. Program execution is(More)
In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which(More)
A handheld neutron-detection sensor application is described in this paper. The sensor system utilizes a new class of boron carbide diode that interacts with incoming neutrons. To interface with the boron carbide diode, an integrated front end is designed in a 1.5-μm standard CMOS technology. With the diode and front-end microchip, a handheld(More)