This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyp-ing and design environment for communication and digital signal processing (DSP) systems, consisting of four multi-FPGA based processing units, each capable of emulating 10 million ASIC… (More)
A system-level perspective of a hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. Capturing design decisions in a dataflow graph allows pushbutton automation of layout and performance estimation. A detailed example of the design process for a DSSS TDMA baseband receiver is presented.
The rapid proliferation of high bandwidth communications systems operating in low signal-to-noise ratio (SNR) environments continue to push systems designers to invent new algorithms that approach the Shannon capacity. The design and testing of these algorithms, whether in hardware or software has traditionally been a time consuming task especially as bit… (More)